1. Field of the Invention
The present invention relates to a low amplitude differential output circuit, and more particularly relates to a low amplitude differential output circuit and a serial transmission interface using the same.
2. Description of the Related Art
In recent years, in a field such as the clustering in a server and the connection of the server to an external storage, requiring communication at a super high speed, a serial interface technique represented by InfiniBand (registered trademark) has been widely used. In many cases, a differential output circuit is used for transmission of a signal through a transmission path between integrated circuits or between apparatuses at a high speed.
When the differential output circuit is used, a technique is demanded in which a central voltage of a differential signal to be transmitted, a so-called VCM (Common Mode Voltage) is reduced, in order to suppress EMI (Electric Magnetic Interference) and crosstalk between the transmission paths adjacent to each other. The value of the VCM is defined, for example, in PCI Express (registered trademark) and the InfiniBand (registered trademark), which are the typical examples of the differential interface. Also, in the differential output circuit, great importance is in the fact that an electric power is low and a circuit size is small, in order to suppress power consumption and a chip cost.
One example of the differential output circuit according to the conventional technique will be described below with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a configuration of the conventional differential output circuit, and FIG. 2 is a diagram showing the configuration of a pre-buffer output circuit.
With reference to FIG. 1, the conventional differential output circuit includes a pre-buffer 100 for outputting a main buffer drive signal MINT/MINB, which is a differential signal for driving a main buffer 200, from an input single phase signal IN; and the main buffer 200 which is connected to the pre-buffer 100 and outputs a differential output signal of signals OUTT/OUTB corresponding to the signal levels of the main buffer drive signal MINT/MINB. The pre-buffer 100 includes CMOS circuits 101 and 102 for generating the differential input signal DINT/DINB from the input single phase signal IN; and a pre-buffer output circuit 103 for outputting the main buffer drive signal MINT/MINB for driving the main buffer 200 having a large transistor size. The pre-buffer output circuit 103 includes a CMOS circuit 105 to which a positive phase input signal DINT of the differential input signal DINT/DINB is supplied; and a CMOS circuit 104 to which a negative phase input signal DINB is supplied.
Referring to FIG. 2, the CMOS circuit 104 has a P-channel MOS transistor P11 and an N-channel MOS transistor N22 between a power source voltage VDD and a ground voltage GND and outputs the positive phase drive signal MINT that is an inversion of the negative phase input signal DINB. The CMOS circuit 105 has a P-channel MOS transistor P110 and an N-channel MOS transistor N220 between the power source voltage VDD and the ground voltage GND and outputs the negative phase drive signal MINB that is a inversion of the positive phase input signal DINT. In this way, the pre-buffer 100 outputs to the main buffer 200 a main buffer drive signal MINT/MINB composed of the positive phase drive signal MINT and the negative phase drive signal MINB which are logically opposite to each other.
Referring to FIG. 1 again, the main buffer 200 includes an N-channel MOS transistor N30 to which the positive phase drive signal MINT outputted from the pre-buffer 100 is supplied; and an N-channel MOS transistor N40 to which the negative phase drive signal MINB is supplied. The N-channel MOS transistor N30 and the N-channel MOS transistor N40 are connected through resistors R30 and R40 to the power source voltage VDD, respectively, and connected through a current source N50 to the ground voltage GND. Here, the power source voltage VDD of the main buffer 200 may be different from the power source voltage VDD of the pre-buffer 100. In such a configuration, in the main buffer 200, the ON/OFF states of the N-channel MOS transistor N40 and the N-channel MOS transistor N30 are controlled in accordance with the signal levels of the main buffer drive signal MINT/MINB. The differential output signal OUTT/OUTB composed of the positive phase output signal OUTT and the negative phase output signal OUTB which are outputted from the respective drains of the transistors N40 and 30 are outputted.
As shown in FIG. 2, in the pre-buffer output circuit 103 that uses the CMOS circuits, the variation in Tpd (a delay time between pins) in the differential input signal DINT/DINB and the main buffer drive signal MINT/MINB causes a problem that the VCM of the differential output signal OUTT/OUTB from the main buffer 200 is extremely varied. Also, in the pre-buffer output circuit 103, the CMOS circuit 104 and the CMOS circuit 105, which are independent of each other, output the positive phase drive signal MINT and the negative phase drive signal MINB, respectively. As a result, a skew in the main buffer drive signal MINT/MINB and the like is changed due to the variation in the power source voltage, the temperature, the process and the like, and a cross point between the positive phase drive signal MINT and the negative phase drive signal MINB is changed. Therefore, the stable VCM level cannot be obtained. Moreover, when a full swing signal to the power source voltage VDD of the CMOS circuit is sent to this differential output circuit, it is difficult to adjust the cross point of the positive phase drive signal MINT and the negative phase drive signal MINB to the operation point of the differential output circuit.
FIGS. 3A to 3C, 4A to 4C, 5A to 5C and 6A to 6C show the signal waveforms of the differential output signals OUTT/OUTB and VCM (OUTT+OUTB) when the main buffer drive signal MINT/MINB whose peak voltages are from the VDD to the GND is supplied to the main buffer 200 in the differential output circuit shown in FIG. 1.
With reference to FIGS. 3A to 3C, when the cross point of the main buffer drive signal MINT/MINB is set to a standard value of VDD/2 at times T31, T32, T33, T34 and so on, the cross points (the times T31, T32, T33, T34 and so on) of the differential output signal OUTT/OUTB is always on the high voltage side. When the differential output signal OUTT/OUTB is shifted, the VCM is varied to an undesirable value (exceeding an allowable range defined by a rule or the like).
FIGS. 4A to 4C shows the waveforms of the main buffer drive signal MINT/MINB, the differential output signal OUTT/OUTB and the VCM, when the positive phase drive signal MINT of the pre-buffer output circuit 103 is delayed rather than the negative phase drive signal MINB. In this case, the falling time from a high level to a low level in the positive phase drive signal MINT or the rising time from the low level to the high level is always delayed than the rising time from the low level to the high level in the negative phase drive signal MINB or the falling time from the high level to the low level. Thus, the cross point of the main buffer drive signal MINT/MINB is on a high voltage side (VDD side) at times T41, T43, T45 and so on, and the cross point is on a low voltage side (GND side) at times T42, T44, T46 and so on. Thus, the cross points of the differential output signal OUTT/OUTB are alternately varied between the high voltage side (the times T42, T44 and so on) and the middle point (the times T41, T43 and so on) between the high level and the low level. When the cross points of the differential output signal OUTT OUTB are located near the middle point (the times T41, T43 and so on), the VCM is varied at the value within a ruled allowable range. However, when the cross points of the differential output signal OUTT/OUTB are on the high voltage side (the times T42, T44 and so on), the VCM is varied in an undesirable range.
FIGS. 5A to 5C shows the time charts of the main buffer drive signal MINT/MINB, the differential output signal OUTT/OUTB and the VCM when the positive phase drive signal MINT of the pre-buffer output circuit 103 is advanced from the negative phase drive signal MINB. In this case, the falling time from the high level to the low level in the positive phase drive signal MINT or the rising time from the low level to the high level is always advanced from the rising time from the low level to the high level in the negative phase drive signal MINB or the falling time from the high level to the low level. Thus, the cross points of the main buffer drive signal MINT/MINB are on the low voltage side (the GND side) at times T51, T53 and so on and on the high voltage side (the VDD side) at times T52, T54 and so on. Therefore, the cross points of the differential output signal OUTT/OUTB are alternately varied between the high voltage side (the times T51, T53, T55 and so on) and the middle point (T52, T54, T56 and so on) between the high level and the low level. When the cross points of the differential output signal OUTT/OUTB are located near the middle points (the times T52, T54, T56 and so on), the VCM is varied in the ruled allowable range. However, when the cross points of the differential output signal OUTT/OUTB are on the high voltage side (the times T51, T53, T55 and so on), the VCM is varied in an undesirable range.
FIGS. 6A to 6C show the waveforms of the main buffer drive signal MINT/MINB, the differential output signal OUTT/OUTB and the VCM, when the duty of the positive phase drive signal MINT in the pre-buffer output circuit 103 is shifted to the negative phase drive signal MINB. In this case, in the main buffer drive signal MINT/MINB, the rising time from the low level to the high level is always delayed than the falling time from the high level to the low level. Thus, the cross points of the main buffer drive signal MINT/MINB are always on the low voltage side (GND side) at times T61, T62, T63, T64 and so on. Therefore, at the times T61, T62, T63, T64 and so on, the cross points of the differential output signal OUTT/OUTB are always on the high voltage side. At this time, the VCM is varied to the worst value, as compared with the variations in the VCM shown in FIGS. 3A to 3C, 4A to 4C and 5A to 5C.
FIG. 7 shows one example of a configuration of another conventional differential output circuit using a differential CML circuit. The differential output circuit includes a pre-buffer 110 for generating the main buffer drive signal MINT/MINB which is a differential signal to drive a main buffer 210, from an input single phase signal IN; and the main buffer 210 which is connected to the pre-buffer 110 and outputs the differential output signal OUTT/OUTB corresponding to the signal levels of the main buffer drive signal MINT/MINB. The pre-buffer 110 includes a CMOS circuit 111 and a converter 112 which generates a differential input signal DINT/DINB from the single phase signal IN; and a differential CML 113 for outputting the main buffer drive signal MINT/MINB to drive the main buffer 210 whose transistor size is large. The converter 112 decreases a full swing level of VDD to about ½ of the power supply voltage VDD for the CMOS circuit 111, and outputs the main buffer drive signal MINT/MINB. In such a configuration, the pre-buffer 110 outputs the main buffer drive signal MINT/MINB, which is composed of the positive phase drive signal MINT and the negative phase drive signal MINB that are opposite in phase to each other, to the main buffer 210. The main buffer 210 has the same structure as the above main buffer 200 and includes an N-channel MOS transistor N41 to which the positive phase drive signal MINT outputted from the pre-buffer 110 is supplied; and an N-channel MOS transistor N31 to which the negative phase drive signal MINB is supplied. The N-channel MOS transistor N31 and the N-channel MOS transistor N41 are connected to the power source voltage VDD through resistors R31 and R41, respectively, and connected through a current source N51 to the ground voltage GND. In such a configuration, in the main buffer 210, ON and OFF of the N-channel MOS transistor N31 and the N-channel MOS transistor N41 are controlled in accordance with the signal levels of the main buffer drive signal MINT/MINB, and the differential output signal OUTT/OUTB composed of the positive phase output signal OUTT and the negative phase output signal OUTB is outputted from the respective drains of the transistors.
With reference to FIGS. 8A to 8C, typically, the CML circuit uses a stable constant current. Thus, even if the variation in the power source voltage, the temperature, the process or the like is caused, the cross points of the main buffer drive signal MINT/MINB outputted from the CML circuit can be adjusted to the vicinity of the operation point of the main buffer 210. At times T81, T82, T83, T84 and so on, the cross points of the differential output signal OUTT/OUTB are always located near the middle point between the high level and the low level. At this time, a relatively small variation is attained in the VCM.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-A-Heisei, 7-273619) discloses a conventional buffer circuit that can prevent the generation of skew and reduce a timing margin. In this conventional buffer circuit, between an output of a CMOS inverter constituting an input gate stage and an input of the CMOS inverter serving as the same phase output gate stage, a push-pull circuit is provided to output a signal having the same phase as the output signal of the CMOS inverter in parallel to the CMOS inverter as a signal route, and the numbers of the gate stages to the same phase output and the negative phase output are made equal. As a result, the delay time between the same phase output and the negative phase output is removed, thereby preventing the generation of the skew.
In the differential output circuit using the CMOS circuit, when the cross points of the main buffer drive signal MINT/MINB are on the high voltage side, the cross points of the differential output signal OUTT/OUTB are located near the middle point between the high level and the low level, and the VCM variation generated at this time is within the allowable range defined by the rule. However, in the differential output circuit shown in FIG. 2, it is difficult to consider the variations in the power source voltage, the temperature, the process and the like, maintain the cross points of the main buffer drive signal MINT/MINB on the high voltage side, and reduce the VCM variation. For example, in case of the differential output circuit used in a SerDes circuit, the inventor of the present invention confirmed the fact that, although VCM=25 mV (rms) is defined in PCI Express and InfiniBand, the maximum value of the VCM variation is 51 mV actually.
Also, in case of the differential output circuit using the CLM circuit, electric power consumption and circuit size in the pre-buffer 110 become greater. It causes increase in price containing a package that this circuit is installed in a macro such as a high speed serial interface macro occupying the majority of a chip and having a large electric consumption power. Therefore, the differential output circuit using this kind of CML circuit is not practicable. For example, when this differential output circuit is used in the high speed serial interface macro, the VCM variation is 10 mV (rms) although the definition is 25 mV (rms). This indicates the variation within the allowable range. In this case, however, the inventor of the present invention confirmed that the electric power consumption is about four times as compared with the conventional example using the CMOS circuit, and the macro area is about ten times.